R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 257

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Note:
Bit
31 to 17
16
15 to 10
9
8
7 to 2
1
0
* The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Bit Name
⎯
LE
⎯
W3LOAD*
W3LOCK
⎯
W2LOAD*
W2LOCK
Initial
Value
All 0
0
All 0
0
0
All 0
0
0
R/W
R
R/W
R
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Lock Enable
Controls the cache locking function.
0: Not cache locking mode
1: Cache locking mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Way 3 Load
Way 3 Lock
When a cache miss occurs by the prefetch instruction
while W3LOAD = 1 and W3LOCK = 1 in cache locking
mode, the data is always loaded into way 3. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
Reserved
These bits are always read as 0. The write value should
always be 0.
Way 2 Load
Way 2 Lock
When a cache miss occurs by the prefetch instruction
while W2LOAD = 1 and W2LOCK =1 in cache locking
mode, the data is always loaded into way 2. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
Rev. 3.00 Sep. 28, 2009 Page 225 of 1650
REJ09B0313-0300
Section 8 Cache