R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1236

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 23 USB 2.0 Host/Function Module (USB)
(a)
Table 23.20 shows the pipes that can be selected with the various FIFO ports. The pipe to be
accessed is selected using the CURPIPE bit in C/DnFIFOSEL. After the pipe has been selected,
FRDY = 1 should be confirmed before accessing the FIFO port.
Also, the bus width to be accessed should be selected using the MBW bit. The buffer memory
access direction conforms to the DIR bit in PIPEnCFG. The ISEL bit determines this only for the
DCP.
Table 23.20 FIFO Port Access Categorized by Pipe
(b)
It is possible to temporarily stop access to the pipe currently being accessed, access a different
pipe, and then continue processing using the current pipe once again. The REW bit in
C/DnFIFOSEL is used for this.
If a pipe is selected when the REW bit is set to 1 and at the same time the CURPIPE bit in
C/DnFIFOSEL is set, the pointer used for reading from and writing to the buffer memory is reset,
and reading or writing can be carried out from the first byte. Also, if a pipe is selected with 0 set
for the REW bit, data can be read and written in continuation of the previous selection, without the
pointer used for reading from and writing to the buffer memory being reset.
To access the FIFO port, FRDY = 1 must be confirmed after selecting a pipe.
(c)
Even in the FRDY = 0 state, when data cannot be read from the buffer memory, confirming the
SBUSY bit in CFIFOSIE and setting 1 for the TGL bit makes it possible for this module to read
and access data on the SIE side. PID = NAK should be set and SBUSY = 0 confirmed, and then
TGL = 1 written. This module is then able to read data from CFIFO. This function can be used
only in the buffer memory reading direction. Also, the BRDY interrupt is generated by operation
of the TGL bit.
Rev. 3.00 Sep. 28, 2009 Page 1204 of 1650
REJ09B0313-0300
Pipe
DCP
PIPE1 to PIPE7
FIFO Port Selection
REW Bit
Reading the Buffer Memory on the SIE (CFIFO Port Reading Direction)
Access Method
CPU access
CPU access
DMA access
D0FIFO/D1FIFO port register
Port that can be Used
CFIFO port register
CFIFO port register
D0FIFO/D1FIFO port register