R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 308

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 9 Bus State Controller (BSC)
• CS3WCR
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 276 of 1650
REJ09B0313-0300
Bit
31 to 15
14, 13
Note:
R/W:
R/W:
Bit:
Bit:
*
If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are
used in both areas in common.
31
15
R
R
0
0
Bit Name
⎯
WTRP[1:0]*
-
-
R/W
WTRP[1:0]*
30
14
R
0
0
-
R/W
29
13
R
0
0
-
Initial
Value
All 0
00
28
12
R
R
0
0
-
-
WTRCD[1:0]*
R/W
27
11
R
0
0
-
R/W
R/W
R
R/W
26
10
R
0
1
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Auto-Precharge Completion Wait Cycles
Specify the number of minimum precharge completion
wait cycles as shown below.
•
•
•
•
•
The setting for areas 2 and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
25
R
R
0
9
0
-
-
From the start of auto-precharge and issuing of
ACTV command for the same bank
From issuing of the PRE/PALL command to issuing
of the ACTV command for the same bank
Till entering the power-down mode or deep power-
down mode
From the issuing of PALL command to issuing REF
command in auto refresh mode
From the issuing of PALL command to issuing
SELF command in self refresh mode
R/W
24
R
0
8
A3CL[1:0]
1
-
R/W
23
R
0
7
0
-
22
R
R
0
6
0
-
-
21
R
R
0
5
0
-
-
R/W
TRWL[1:0]*
20
R
0
4
0
-
R/W
19
R
0
3
0
-
18
R
R
0
2
0
-
-
R/W
WTRC[1:0]*
17
R
0
1
0
-
R/W
16
R
0
0
0
-