R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 855

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

16.4.7
In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1)
Figure 16.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
Figure 16.12 Example of Initial Settings in Clock Synchronous Communication Mode
Initial Settings in Clock Synchronous Communication Mode
[1]
[2]
[3]
[4]
[5]
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Clock Synchronous Communication Mode
Set the SSUMS bit in SSCRL to 1 and
Clear the TE and RE bits in SSER to 0
Specify the CPOS, CKS2, CKS1, and
Set PFC for external pins to be used
Specify the TEIE, TIE, RIE, TE, RE
and CEIE bits in SSER all together
specify bits DATS1 and DATS0
Specify the MSS bit in SSCRH
(SSCK, SSI, SSO, and SCS)
Start setting initial values
CKS0 bits in SSMR
End
Section 16 Synchronous Serial Communication Unit (SSU)
[1] Make appropriate settings in the PFC for the external
[2] Specify master/slave mode selection and SSCK pin
[3] Selects clock synchronous communication mode and
[4] Specify clock polarity selection and transfer clock rate
[5] Enables/disables interrupt request to the CPU.
pins to be used.
selection.
specify transmit/receive data length.
selection.
Rev. 3.00 Sep. 28, 2009 Page 823 of 1650
REJ09B0313-0300