R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 899

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

No
No
No
Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set RCVD in ICCR1 to 1
Master receive mode
Dummy-read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Clear TEND in ICSR
Clear TDRE in ICSR
Read STOP in ICSR
Clear STOP in ICSR
Write 0 to BBSY
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
and SCP
End
- 1?
Yes
Yes
Yes
Figure 17.19 Sample Flowchart for Master Receive Mode
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
Notes: 1. Make sure that no interrupt will be generated during steps [1] to [3].
Clear TEND, select master receive mode, and then clear TDRE. *
Set acknowledge to the transmit device. *
Dummy-read ICDDR. *
Wait for 1 byte to be received *
Check whether it is the (last receive - 1). *
Read the receive data.
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). *
Read the (final byte - 1) of received data.
Wait for the last byte to be receive.
2. At the stage of the (last reception - 1) (i.e. when the decision at [5]
When the size of receive data is only one byte in reception,
The step [8] is dummy-read in ICDRR.
steps [2] to [6] are skipped after step [1], before jumping to step [7].
has been satisfied), make sure that interrupts are not generated
during the steps of [4], [5], and [7].
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Rev. 3.00 Sep. 28, 2009 Page 867 of 1650
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Section 17 I
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C Bus Interface 3 (IIC3)
REJ09B0313-0300
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