R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 27

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

23.4 Operation ......................................................................................................................... 1170
23.5 Usage Notes ..................................................................................................................... 1230
Section 24 LCD Controller (LCDC)................................................................1233
24.1 Features............................................................................................................................ 1233
24.2 Input/Output Pins ............................................................................................................. 1235
24.3 Register Configuration..................................................................................................... 1236
23.3.27 USB Request Length Register (USBLENG) .................................................... 1152
23.3.28 DCP Configuration Register (DCPCFG) .......................................................... 1153
23.3.29 DCP Maximum Packet Size Register (DCPMAXP)......................................... 1155
23.3.30 DCP Control Register (DCPCTR) .................................................................... 1156
23.3.31 Pipe Window Select Register (PIPESEL)......................................................... 1158
23.3.32 Pipe Configuration Register (PIPECFG) .......................................................... 1159
23.3.33 Pipe Buffer Setting Register (PIPEBUF) .......................................................... 1162
23.3.34 Pipe Maximum Packet Size Register (PIPEMAXP)......................................... 1164
23.3.35 Pipe Timing Control Register (PIPEPERI)....................................................... 1165
23.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 7)........................................... 1167
23.3.37 USB AC Characteristics Switching Register (USBACSWR)........................... 1169
23.4.1
23.4.2
23.4.3
23.4.4
23.4.5
23.4.6
23.4.7
23.4.8
23.4.9
23.4.10 Pipe Schedule.................................................................................................... 1228
23.5.1
23.5.2
23.5.3
24.3.1
24.3.2
24.3.3
24.3.4
24.3.5
24.3.6
24.3.7
24.3.8
24.3.9
System Control ................................................................................................. 1170
Interrupt Functions............................................................................................ 1172
Pipe Control ...................................................................................................... 1190
Buffer Memory ................................................................................................. 1197
Control Transfers (DCP)................................................................................... 1213
Bulk Transfers (PIPE1 to PIPE5)...................................................................... 1216
Interrupt Transfers (PIPE6 and PIPE7)............................................................. 1218
Isochronous Transfers (PIPE1 and PIPE2) ....................................................... 1219
SOF Interpolation Function .............................................................................. 1226
Note on Using Isochronous OUT Transfer ....................................................... 1230
Procedure for Setting the USB Transceiver ...................................................... 1231
Timing for the Clearing of Interrupt Sources.................................................... 1232
LCDC Input Clock Register (LDICKR) ........................................................... 1237
LCDC Module Type Register (LDMTR) ......................................................... 1239
LCDC Data Format Register (LDDFR) ............................................................ 1242
LCDC Scan Mode Register (LDSMR) ............................................................. 1244
LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ....... 1246
LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ....... 1247
LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ....... 1248
LCDC Palette Control Register (LDPALCR)................................................... 1249
Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ................................... 1250
Rev. 3.00 Sep. 28, 2009 Page xxv of xxx
REJ09B0313-0300