R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1673

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Numerics
16-bit/32-bit displacement ........................ 57
A
A/D conversion time
(multi mode and scan mode)................. 1038
A/D conversion time (single mode)...... 1037
A/D conversion timing ......................... 1037
A/D converter (ADC) ........................... 1019
A/D converter activation......................... 601
A/D converter characteristics................ 1604
A/D converter start request delaying
function................................................... 594
Absolute address....................................... 57
Absolute address accessing....................... 57
Absolute maximum ratings................... 1521
AC characteristics................................. 1531
AC characteristics measurement
conditions.............................................. 1603
Access size and data alignment .............. 297
Access wait control................................. 309
ADC timing .......................................... 1587
Address array.................................. 220, 234
Address array read .................................. 234
Address errors......................................... 133
Address map ........................................... 244
Address multiplexing.............................. 320
Address spaces of on-chip high-speed
RAM ..................................................... 1393
Address spaces of on-chip RAM for
data retention ........................................ 1393
Address-array write
(associative operation) ............................ 235
Address-array write
(non-associative operation)..................... 234
Addressing modes..................................... 58
Analog input pin ratings ....................... 1043
Index
AND/NAND flash memory controller
(FLCTL)................................................ 1053
Arithmetic operation instructions.............. 77
Auto-refreshing ....................................... 347
Auto-request mode.................................. 423
B
Bank active ............................................. 340
Banked register and input/output of
banks ....................................................... 189
BCHG interrupt..................................... 1189
BEMP interrupt..................................... 1183
Bit manipulation instructions .................... 88
Bit synchronous circuit ........................... 871
Branch instructions ................................... 82
BRDY interrupt..................................... 1176
Break detection and processing............... 787
Break on data access cycle...................... 212
Break on instruction fetch cycle.............. 211
Buffer memory...................................... 1197
Bulk transfers ........................................ 1216
Burst mode.............................................. 437
Burst MPX-I/O interface......................... 374
Burst read ................................................ 332
Burst ROM (clocked asynchronous)
interface .................................................. 360
Burst ROM (clocked synchronous)
interface .................................................. 379
Burst write............................................... 337
Bus arbitration......................................... 387
Bus format for SSI module ..................... 892
Bus state controller (BSC) ...................... 239
Bus timing............................................. 1539
Bus-released state...................................... 91
C
Cache ...................................................... 219
Rev. 3.00 Sep. 28, 2009 Page 1641 of 1650
REJ09B0313-0300