R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 795

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

15.4
15.4.1
For serial communication, the SCIF has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses.
The SCIF has a 16-stage FIFO buffer for both transmission and receptions, reducing the overhead
of the CPU, and enabling continuous high-speed communication. Furthermore, channel 3 has RTS
and CTS signals to be used as modem control signals.
The transmission format is selected in the serial mode register (SCSMR), as shown in table 15.9.
The SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial
control register (SCSCR), as shown in table 15.10.
(1)
• Data length is selectable: 7 or 8 bits
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding
• In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full,
• The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
• An internal or external clock can be selected as the SCIF clock source.
selections constitutes the communication format and character length.
overrun errors, receive data ready, and breaks.
⎯ When an internal clock is selected, the SCIF operates using the clock of on-chip baud rate
⎯ When an external clock is selected, the external clock input must have a frequency 16 or 8
Asynchronous Mode
generator.
times the bit rate. (The on-chip baud rate generator is not used.)
Operation
Overview
Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 763 of 1650
REJ09B0313-0300