R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1393
R0K572030S000BE
Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K572030S000BE
Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
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25.2.12 SSI Oversampling Clock Selection Register (SCSR)
SCSR is a 16-bit readable/writable register that selects the clock source and division ratio of
oversampling clock used in the SSI.
Initial value:
Bit
15
14 to 12
11
10 to 8
7
6 to 4
3
R/W:
Bit:
Bit Name
⎯
SSI3CKS
[2:0]
⎯
SSI2CKS
[2:0]
⎯
SSI1CKS
[2:0]
⎯
15
R
0
-
R/W
14
0
SSI3CKS[2:0]
R/W
13
0
Initial
Value
0
000
0
000
0
000
0
R/W
12
0
11
R
0
-
R/W
R
R/W
R
R/W
R
R/W
R
R/W
10
0
SSI2CKS[2:0]
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
SSI ch3 Clock Select
Select the source of the oversampling clock that is
used in channel 3 of the SSI. For settings, see table
25.8.
Reserved
This bit is always read as 0. The write value should
always be 0.
SSI ch2 Clock Select
Select the source of the oversampling clock that is
used in channel 2 of the SSI. For settings, see table
25.8.
Reserved
This bit is always read as 0. The write value should
always be 0.
SSI ch1 Clock Select
Select the source of the oversampling clock that is
used in channel 1 of the SSI. For settings, see table
25.8.
Reserved
This bit is always read as 0. The write value should
always be 0.
9
0
R/W
8
0
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 1361 of 1650
R/W
Section 25 Pin Function Controller (PFC)
6
0
SSI1CKS[2:0]
R/W
5
0
R/W
4
0
R
3
0
-
REJ09B0313-0300
R/W
2
0
SSI0CKS[2:0]
R/W
1
0
R/W
0
0
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