R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 720

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 13 Watchdog Timer (WDT)

Pay attention to the following points when using the WDT in either the interval timer or watchdog

After timer operation has started, the period from the power-on reset point to the first count up

timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The

shortest such time period is thus one cycle of the peripheral clock, Pφ, while the longest is the

result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent

incrementation is in accord with the selected frequency division ratio. Accordingly, this time

difference is referred to as timer variation.

This also applies to the timing of the first incrementation after WTCNT has been written to during

timer operation.

When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred.

Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or WDT reset will occur

immediately, regardless of the current clock selection by the CKS[2:0] bits.

When the value in WTCNT is H'FF, the IOVF flag in WTCSR cannot be cleared.

Only clear the IOVF flag when the value in WTCNT has either become H'00 or been changed to a

value other than H'FF.

Rev. 3.00 Sep. 28, 2009 Page 688 of 1650

REJ09B0313-0300

Timer Variation

Prohibition against Setting H'FF to WTCNT

Interval Timer Overflow Flag