R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 81

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

(2)
GBR is referenced as the base address in a GBR-referencing MOV instruction.
(3)
VBR is referenced as the branch destination base address in the event of an exception or an
interrupt.
(4)
TBR is referenced as the start address of a function table located in memory in a
JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.
Bit
31 to 15 —
14
13
12 to 10 —
9
8
7 to 4
3, 2
1
0
Global Base Register (GBR)
Vector Base Register (VBR)
Jump Table Base Register (TBR)
Bit Name Initial Value
BO
CS
M
Q
I[3:0]
—
S
T
All 0
0
0
All 0
—
—
1111
All 0
—
—
R
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
BO Bit
Indicates that a register bank has overflowed.
CS Bit
Indicates that, in CLIP instruction execution, the value
has exceeded the saturation upper-limit value or
fallen below the saturation lower-limit value.
Reserved
These bits are always read as 0. The write value
should always be 0.
M Bit
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Interrupt Mask Level
Reserved
These bits are always read as 0. The write value
should always be 0.
S Bit
Specifies a saturation operation for a MAC
instruction.
T Bit
True/false condition or carry/borrow bit
Rev. 3.00 Sep. 28, 2009 Page 49 of 1650
REJ09B0313-0300
Section 2 CPU