R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 712

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 13 Watchdog Timer (WDT)
Rev. 3.00 Sep. 28, 2009 Page 680 of 1650
REJ09B0313-0300
Bit
5
4, 3
2 to 0
Bit Name
TME
⎯
CKS[2:0]
Initial
Value
0
All 1
000
R/W
R/W
R
R/W
Description
Timer Enable
Starts and stops timer operation. Clear this bit to 0
when using the WDT in software standby mode or
when changing the clock frequency.
0: Timer disabled
1: Timer enabled
Reserved
These bits are always read as 1. The write value
should always be 1.
Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is
shown inside the parenthesis in the table is the value
when the peripheral clock (Pφ) is 33 MHz.
Note: If bits CKS[2:0] are modified when the WDT is
Bits 2 to 0
000:
001:
010:
011:
100:
101:
110:
111:
Count-up stops and WTCNT value is retained
running, the up-count may not be performed
correctly. Ensure that these bits are modified
only when the WDT is not running.
Clock Ratio
1 × Pφ
1/64 × Pφ
1/128 × Pφ
1/256 × Pφ
1/512 × Pφ
1/1024 × Pφ
1/4096 × Pφ
1/16384 × Pφ
Overflow Cycle
7.7 μs
500 μs
1.0 ms
2.0 ms
4.0 ms
8.0 ms
32 ms
128 ms