R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 282

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 9 Bus State Controller (BSC)
9.4.2
CSnBCR is a 32-bit readable/writable register that specifies the function of each area, the number
of idle cycles between bus cycles, and the bus width.
Do not access external memory other than area 0 until CSnBCR initial setting is completed.
Idle cycles may be inserted even when they are not specified. For details, see section 9.5.12, Wait
between Access Cycles.
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 250 of 1650
REJ09B0313-0300
Bit
31
30 to 28 IWW[2:0]
Note:
R/W:
R/W:
Bit:
Bit:
*
CSn Space Bus Control Register (CSnBCR) (n = 0 to 7)
CSnBCR samples the external pin (MD) that specify the bus width at power-on reset.
Bit Name
⎯
31
15
R
R
0
0
-
-
R/W
R/W
30
14
0
0
TYPE[2:0]
IWW[2:0]
R/W
R/W
29
13
1
0
Initial
Value
0
011
R/W
R/W
28
12
1
0
ENDIAN
R/W
R/W
27
11
0
0
R/W
R
R/W
IWRWD[2:0]
R/W
R/W
26
10
1*
1
BSZ[1:0]
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Idle Cycles between Write-Read Cycles and Write-
Write Cycles
These bits specify the number of idle cycles to be
inserted after the access to a memory that is
connected to the space. The target access cycles are
the write-read cycle and write-write cycle.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
R/W
R/W
25
1*
1
9
R/W
24
R
0
8
0
-
IWRWS[2:0]
R/W
23
R
1
7
0
-
R/W
22
R
1
6
0
-
R/W
21
R
0
5
0
-
IWRRD[2:0]
R/W
20
R
1
4
0
-
R/W
19
R
1
3
0
-
R/W
18
R
0
2
0
-
IWRRS[2:0]
R/W
17
R
1
1
0
-
R/W
16
R
1
0
0
-