R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 588

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.53 Register Settings for Complementary PWM Mode
Note:
Rev. 3.00 Sep. 28, 2009 Page 556 of 1650
REJ09B0313-0300
Channel
3
4
Timer dead time data register
(TDDR)
Timer cycle data register
(TCDR)
Timer cycle buffer register
(TCBR)
Subcounter (TCNTS)
Temporary register 1 (TEMP1)
Temporary register 2 (TEMP2)
Temporary register 3 (TEMP3)
* Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER
(timer read/write enable register).
Counter/Register
TCNT_3
TGRA_3
TGRB_3
TGRC_3
TGRD_3
TCNT_4
TGRA_4
TGRB_4
TGRC_4
TGRD_4
Description
Start of up-count from value set
in dead time register
Set TCNT_3 upper limit value
(1/2 carrier cycle + dead time)
PWM output 1 compare register
TGRA_3 buffer register
PWM output 1/TGRB_3 buffer
register
Up-count start, initialized to
H'0000
PWM output 2 compare register
PWM output 3 compare register
PWM output 2/TGRA_4 buffer
register
PWM output 3/TGRB_4 buffer
register
Set TCNT_4 and TCNT_3 offset
value (dead time value)
Set TCNT_4 upper limit value
(1/2 carrier cycle)
TCDR buffer register
Subcounter for dead time
generation
PWM output 1/TGRB_3
temporary register
PWM output 2/TGRA_4
temporary register
PWM output 3/TGRB_4
temporary register
Read/Write from CPU
Maskable by TRWER
setting*
Maskable by TRWER
setting*
Maskable by TRWER
setting*
Always readable/writable
Always readable/writable
Maskable by TRWER
setting*
Maskable by TRWER
setting*
Maskable by TRWER
setting*
Always readable/writable
Always readable/writable
Maskable by TRWER
setting*
Maskable by TRWER
setting*
Always readable/writable
Read-only
Not readable/writable
Not readable/writable
Not readable/writable