R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 878

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 17 I
17.3.5
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
Rev. 3.00 Sep. 28, 2009 Page 846 of 1650
REJ09B0313-0300
Bit
7
6
I
2
Bit Name
TDRE
TEND
C Bus Status Register (ICSR)
2
C Bus Interface 3 (IIC3)
Initial value:
Initial
Value
0
0
R/W:
Bit:
TDRE
R/W
7
0
R/W
R/W
R/W
TEND
R/W
6
0
Description
Transmit Data Register Empty
[Clearing conditions]
•
•
[Setting conditions]
•
•
•
•
[Clearing conditions]
•
•
[Setting conditions]
•
•
Transmit End
RDRF NACKF STOP AL/OVE
R/W
5
0
When 0 is written in TDRE after reading TDRE = 1
When data is written to ICDRT
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When the start condition (including retransmission)
is issued
When slave mode is changed from receive mode to
transmit mode
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT
When the ninth clock of SCL rises with the I
format while the TDRE flag is 1
When the final bit of transmit frame is sent with the
clocked synchronous serial format
R/W
4
0
R/W
3
0
R/W
2
0
R/W
AAS
1
0
R/W
ADZ
0
0
2
C bus