R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1243

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
Table 23.22 Timing at which BRDY Interrupts are Generated
Note: This function is valid only in the reading direction of reading from the buffer memory. In the
(4)
(a)
Figure 23.15 shows a diagram of the timing up to the point where the FRDY and DTLN bits are
determined when the pipe specified by the FIFO port has been switched (the CURPIPE bit in
C/DnFIFOSEL has been changed).
If the CURPIPE bits have been changed, access to the FIFO port should be carried out after
waiting 450 ns and 8 clock cycles at a peripheral clock after writing to C/DnFIFOSEL.
The same timing applies with respect to the CFIFO port, when the ISEL bit is changed.
Buffer State
When Packet is Received
Buffer full (normal packet received)
Zero-length packet received
Normal short packet received
Transaction count ended
Timing at which the FIFO Port can be Accessed
Timing at which the FIFO Port can be Accessed when Switching Pipes
writing direction, the BFRE bit should be fixed at 0.
Register setting
BFRE = 0
When packet is received
When packet is received
When packet is received
When packet is received
Section 23 USB 2.0 Host/Function Module (USB)
Rev. 3.00 Sep. 28, 2009 Page 1211 of 1650
BFRE = 1
Not generated
When packet is received
When reading of the received
data from the buffer memory
has been completed
When reading of the received
data from the buffer memory
has been completed
REJ09B0313-0300

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