R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 716

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 13 Watchdog Timer (WDT)
13.4
13.4.1
The WDT can be used to cancel software standby mode with an interrupt such as an NMI
interrupt. The procedure is described below. (The WDT does not operate when resets are used for
canceling, so keep the RES or MRES pin low until clock oscillation settles.)
1. Before making a transition to software standby mode, always clear the TME bit in WTCSR
2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the
3. After setting the STBY bit of the standby control register (STBCR: see section 28, Power-
4. The WDT starts counting by detecting the edge change of the NMI signal.
5. When the WDT count overflows, the CPG starts supplying the clock and this LSI resumes
13.4.2
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the
3. When the frequency control register (FRQCR) is written to, this LSI stops temporarily. The
4. When the WDT count overflows, the CPG resumes supplying the clock and this LSI resumes
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to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated
when the count overflows.
counter in WTCNT. These values should ensure that the time till count overflow is longer than
the clock oscillation settling time.
Down Modes) to 1, the execution of a SLEEP instruction puts the system in software standby
mode and clock operation then stops.
operation. The WOVF flag in WRCSR is not set when this happens.
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
counter in WTCNT. These values should ensure that the time till count overflow is longer than
the clock oscillation settling time. However, the WDT counts up using the clock after the
setting.
WDT starts counting.
operation. The WOVF flag in WRCSR is not set when this happens.
WDT Usage
Canceling Software Standby Mode
Changing the Frequency