R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 862

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
Section 16 Synchronous Serial Communication Unit (SSU)
16.5
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive
data register full, and a transmit data register empty can activate the DMAC for data transfer.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 16.8 lists the
interrupt sources.
When an interrupt condition shown in table 16.8 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU or DMAC data transfer.
Table 16.8 SSU Interrupt Sources
Rev. 3.00 Sep. 28, 2009 Page 830 of 1650
REJ09B0313-0300
Abbreviation Interrupt Source
SSERI
SSRXI
SSTXI
SSU Interrupt Sources and DMAC
Overrun error
Conflict error
Receive data register full
Transmit data register empty
Transmit end
Interrupt Condition
(RIE = 1) • (ORER = 1) +
(CEIE = 1) • (CE = 1)
(RIE = 1) • (RDRF = 1)
(TIE = 1) • (TDRE = 1) +
(TEIE = 1) • (TEND = 1)
DMAC Activation
Possible
Possible

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