R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 42

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 1 Overview
1.3
LCD I/F I/O
Rev. 3.00 Sep. 28, 2009 Page 10 of 1650
REJ09B0313-0300
Pin function
Internal LCD bus
debugging
controller
JTAG I/O
interface
(H-UDI)
controller
(PFC)
User
Cache
Port
(IL bus)
CPU core
Block Diagram
SH-2A
General I/O
I/O ports
Power-down
Port
cache memory
control
controller
mode
(LCDC)
Instruction
8 Kbytes
LCD
Clock mode input
Clock pulse
EXTAL input
XTAL output
generator
CKIO I/O
(CPG)
Port
External bus width
On-chip RAM
External bus I/O
(retention)
16 Kbytes
Floating-point
mode input
cache memory
Bus state
controller
unit (FPU)
(BSC)
Port
Operand
8 Kbytes
IRQOUT output
MRES input
PINT input
controller
RES input
MMI input
IRQ input
Interrupt
(INTC)
Port
flash memory
Flash memory
function module
AND/NAND
USB2.0 host/
USB clock input
Figure 1.1 Block Diagram
controller
(FLCTL)
USB bus I/O
I/F I/O
Port
(USB)
On-chip RAM
(high-speed)
Port
64 Kbytes
Timer pulse I/O
Multi-function
timer pulse
(MTU2)
unit 2
Port
D/A converter
Analog output
(DAC)
Port
Compare
match
(CMT)
timer
User break
controller
(UBC)
A/D converter
ADTRG input
bus controller
Analog input
Peripheral
Watchdog
WDTOVF
(ADC)
(WDT)
output
Port
timer
Port
CPU memory access bus (M bus)
CPU instruction fetch bus (F bus)
RTC_X2 output
RTC_X1 input
Realtime
Direct memory
(RTC)
clock
Port
(RCAN-TL1)
CAN bus I/O
Controller
controller
UBCTRG output
(DMAC)
network
access
area
Port
interface with FIFO
communication
Serial I/O
(SCIF)
Serial
Audio clock input
Port
interface
Serial I/O
sound
Serial
(SSI)
Port
Internal DMA bus
Internal CPU bus
DREQ input
DACK output
TEND output
CPU bus
(C bus)
(I clock)
(IC bus)
(ID bus)
Peripheral bus (P clock)
serial commnication
Synchronous
Serial I/O
I
interface 3
(SSU)
2
Port
I
unit
C bus I/O
2
(IIC3)
C bus
Internal bus
Port
(I bus)
(B clock)