R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1229

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 23 USB 2.0 Host/Function Module (USB)

Buffer Memory

Buffer Memory Allocation

Figure 23.9 shows an example of a buffer memory map for this module. The buffer memory is an

area shared by the CPU and this module. In the buffer memory status, there are times when the

access right to the buffer memory is allocated to the user system (CPU side), and times when it is

allocated to this module (SIE side).

The buffer memory sets independent areas for each pipe. In the memory areas, 64 bytes comprise

one block, and the memory areas are set using the first block number of the number of blocks

(specified using the BUFNMB and BUFSIZE bits in PIPEBUF). Moreover, three FIFO ports are

used for access to the buffer memory (reading and writing data). A pipe is assigned to the FIFO

port by specifying the pipe number using the CURPIPE bit in C/DnFIFOSEL.

The buffer statuses of the various pipes can be confirmed using the BSTS bit in DCPCTR and the

INBUFM bit in PIPEnCTR. Also, the access right of the FIFO port can be confirmed using the

FRDY bit in C/DnFIFOCTR.

Rev. 3.00 Sep. 28, 2009 Page 1197 of 1650

REJ09B0313-0300