R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 434

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 10 Direct Memory Access Controller (DMAC)
10.3.2
The DMA destination address registers (DAR) are 32-bit readable/writable registers that specify
the destination address of a DMA transfer. During a DMA transfer, these registers indicate the
next destination address. When the data of an external device with DACK is transferred in single
address mode, DAR is ignored.
To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2-
byte, 4-byte, or16-byte address boundary respectively.
Initial value:
Initial value:
10.3.3
The DMA transfer count registers (DMATCR) are 32-bit readable/writable registers that specify
the number of DMA transfers. The transfer count is 1 when the setting is H'00000001, 16,777,215
when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA
transfer, these registers indicate the remaining transfer count.
The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To
transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one.
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 402 of 1650
REJ09B0313-0300
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
DMA Destination Address Registers (DAR)
DMA Transfer Count Registers (DMATCR)
R/W
R/W
R/W
31
15
31
15
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
30
14
30
14
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
29
13
29
13
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
28
12
28
12
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
27
11
27
11
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
26
10
26
10
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
25
25
R
0
9
0
0
9
0
-
-
-
-
R/W
R/W
R/W
24
24
R
0
8
0
0
8
0
-
-
-
-
R/W
R/W
R/W
R/W
23
23
0
7
0
0
7
0
-
-
-
-
R/W
R/W
R/W
R/W
22
22
0
6
0
0
6
0
-
-
-
-
R/W
R/W
R/W
R/W
21
21
0
5
0
0
5
0
-
-
-
-
R/W
R/W
R/W
R/W
20
20
0
4
0
0
4
0
-
-
-
-
R/W
R/W
R/W
R/W
19
19
0
3
0
0
3
0
-
-
-
-
R/W
R/W
R/W
R/W
18
18
0
2
0
0
2
0
-
-
-
-
R/W
R/W
R/W
R/W
17
17
0
1
0
0
1
0
-
-
-
-
R/W
R/W
R/W
R/W
16
16
0
0
0
0
0
0
-
-
-
-