R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1261

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

This section describes the transfer scheduling within a frame of this module. After the module

sends an SOF, the transfer is carried out in the sequence described below.

1. Execution of periodic transfers

2. Setup transactions for control transfers

3. Execution of bulk and control transfer data stages and status stages

Setting the UACT bit of the DVSTCTR register to 1 initiates sending of an SOF or μSOF, and

makes it possible to generate a transaction.

Setting the UACT bit to 0 stops the sending of the SOF or μSOF and initiates a suspend state. If

the setting of the UACT bit is changed from 1 to 0, processing stops after the next SOF or μSOF is

A pipe is searched in the order of Pipe 1 → Pipe 2 → Pipe 6 → Pipe 7, and then, if the pipe is

one for which an isochronous or interrupt transfer transaction can be generated, the transaction

is generated.

The DCP is checked, and if a setup transaction is possible, it is sent.

A pipe is searched in the order of DCP → Pipe 1 → Pipe 2 → Pipe 3 → Pipe 4 → Pipe 5, and

then, if the pipe is one for which a bulk or control transfer data stage or a control transfer status

stage transaction can be generated, the transaction is generated.

If a transfer is generated, processing moves to the next pipe transaction regardless of whether

the response from the peripheral is ACK or NAK. Also, if there is time for the transfer to be

done within the frame, step 3 is repeated.

Transfer Schedule

USB Communication Enabled

Section 23 USB 2.0 Host/Function Module (USB)

Rev. 3.00 Sep. 28, 2009 Page 1229 of 1650

REJ09B0313-0300