R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 172

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 5 Exception Handling
5.6.2
When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU
operates as follows:
1. The exception service routine start address which corresponds to the vector number specified
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
4. After jumping to the exception service routine start address fetched from the exception
5.6.3
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay
slot. When the instruction placed in the delay slot is undefined code (including FPU instructions
and FPU-related CPU instructions in FPU module standby state), an instruction that rewrites the
PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction, slot
illegal exception handling starts when such kind of instruction is decoded. When the FPU has
entered a module standby state, the floating point operation instruction and FPU-related CPU
instructions are handled as undefined codes. If these instructions are placed in a delay slot and
then decoded, a slot illegal instruction exception handling starts.
The CPU operates as follows:
1. The exception service routine start address is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
4. After jumping to the exception service routine start address fetched from the exception
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in the TRAPA instruction is fetched from the exception handling vector table.
instruction to be executed after the TRAPA instruction.
handling vector table, program execution starts. The jump that occurs is not a delayed branch.
delayed branch instruction immediately before the undefined code, the instruction that rewrites
the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU
instruction.
handling vector table, program execution starts. The jump that occurs is not a delayed branch.
Trap Instructions
Slot Illegal Instructions