R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1287

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

24.3.14 LCDC Vertical Sync Signal Register (LDVSYNR)
LDVSYNR specifies the vertical (scan direction and vertical direction) sync signal timing of the
LCD module.
Initial value:
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W:
Bit:
VSYNW
R/W
15
3
0
Bit Name
VSYNW3
VSYNW2
VSYNW1
VSYNW0
⎯
VSYNP10
VSYNP9
VSYNP8
VSYNP7
VSYNP6
VSYNP5
VSYNP4
VSYNP3
VSYNP2
VSYNP1
VSYNP0
VSYNW
R/W
14
0
2
VSYNW
R/W
13
0
1
Initial
Value
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
VSYNW
R/W
12
0
0
11
R
0
-
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VSYNP
R/W
10
10
0
Description
Vertical Sync Signal Width
Set the width of the vertical sync signals (FLM and
Vsync) (unit: line).
Specify to the value of (the vertical sync signal width) -1.
Example: For a vertical sync signal width of 1 line.
Reserved
This bit is always read as 0. The write value should
always be 0.
Vertical Sync Signal Output Position
Set the output position of the vertical sync signals (FLM
and Vsync) (unit: line).
Specify to the value of (the number of vertical sync signal
output position) -2.
DSTN should be set to an odd number value. It is
handled as (setting value+1)/2.
Example: For an 480-line LCD module and a vertical
retrace period of 0 lines (in other words, VTLN=479 and
the vertical sync signal is active for the first line):
•
•
VSYNP
R/W
9
0
9
Single display
VSYNP = [(1-1)+VTLN]mod(VTLN+1)
Dual displays
VSYNP = [(1-1)×2+VTLN]mod(VTLN+1)
VSYNP
R/W
8
1
8
VSYNW = (1-1) = 0 = H'0
= [(1-1)+479]mod(479+1)
= 479mod480 = 479 =H'1DF
= [(1-1)×2+479]mod(479+1)
= 479mod480 = 479 =H'1DF
VSYNP
R/W
7
1
7
Rev. 3.00 Sep. 28, 2009 Page 1255 of 1650
VSYNP
R/W
6
1
6
VSYNP
R/W
Section 24 LCD Controller (LCDC)
5
0
5
VSYNP
R/W
4
1
4
VSYNP
R/W
3
1
3
VSYNP
REJ09B0313-0300
R/W
2
1
2
VSYNP
R/W
1
1
1
VSYNP
R/W
0
1
0