MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 998

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller
Table 15-6
15-12
0–23
Bits
24
25
26
27
28
29
30
31
EOLNI End-of-links interrupt. After transferring the last block of data in the last link descriptor, if MR n [EOLSIE] is set,
EOLSI End-of-list interrupt. After transferring the last block of data in the last list descriptor, if MR n [EOLSIE] is set,
Name
EOSI End-of-segment interrupt. In chaining mode, after finishing a data transfer, if MR n [EOSIE] is set or if
CH
CB
TE
PE
—
—
describes the bits of the SRn.
Reserved
Transfer error (Bit reset, write 1 to clear)
0 No error condition during the DMA transfer
1 Error condition during the DMA transfer. See
Reserved
Channel halted. Cleared automatically by hardware if MR n [CS] is set again for resuming a halted transfer
0 Channel is not halted. If software attempts to halt an idle channel (SR n [CB] is cleared), this bit remains 0.
1 DMA transfer was successfully halted by software and can be resumed.
Programming error (bit reset, write 1 to clear)
0 No programming error detected
1 A programming error is detected that prevents the DMA transfer from occurring.
then this bit is set and an interrupt is generated.
(Bit reset, write 1 to clear)
Channel busy
0 DMA transfer is finished, an error occurred, or a channel abort occurred.
1 DMA transfer is currently in progress.
CLNDAR n [EOSIE] is set, this bit gets set and an interrupt is generated. In direct mode, if MRn[EOSIE] is set,
this bit gets set and an interrupt is generated.
(Bit reset, write 1 to clear)
then this bit is set and an interrupt is generated.
(Bit reset, write 1 to clear)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 15-6. SR n Field Descriptions
Description
Section 15.4.3, “DMA Errors,”
for additional information.
Freescale Semiconductor