MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 983

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
This advertises to the Link Partner that the TBI supports PAUSE and Full Duplex mode and does not support Half Duplex
Set up the MII Mgmt for a write cycle to TBI’s AN Advertisement register (write the PHY address and Register address),
Set up the MII Mgmt for a read cycle to TBI’s Control register (write the PHY address and Register address),
Set up the MII Mgmt for a write cycle to TBI’s Control register (write the PHY address and Register address),
Set up the MII Mgmt for a write cycle to TBICON register (write the PHY address and Register address),
set source clock divide by 14 for example to insure that MDC clock speed is not greater than 2.5 MHz
This sets TBI in single clock mode and MII Mode off to enable communication with SerDes.
Writing to MII Mgmt Control with 16-bit data intended for TBI’s AN Advertisement register,
Perform an MII Mgmt read cycle to verify state of TBI Control Register (optional)
The AN Advertisement register is at offset address 0x04 from the TBI’s address.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-192. SGMII Mode Register Initialization Steps (continued)
(Uses the TBI address and Register address placed in MIIMADD register),
Writing to MII Mgmt Control with 16-bit data intended for TBICON register,
the control register (CR) is at offset address 0x00 from the TBI’s address.
the control register (CR) is at offset address 0x00 from the TBI’s address.
The TBICON register is at offset address 0x11 from the TBI’s address.
read the MIIMSTAT and look for AN Enable and other bit information.
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_0000_0000_0010_0000]
MIIMCON[0000_0000_0000_0000_0000_0001_1010_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0001_0001]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0100]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
MIIMCFG[0000_0000_0000_0000_000_0000_0000_0101]
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Perform an MII Mgmt write cycle to TBI.
Perform an MII Mgmt write cycle to TBI.
Assign a Physical address to the TBI,
Additional SerDes setup as required
Setup the MII Mgmt clock speed,
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
set to 16, for example.
mode.
Enhanced Three-Speed Ethernet Controllers
14-235