MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 127

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.3.7
The DDR memory controller supports DDR2 and DDR3 SDRAM. The memory interface controls main
memory accesses and provides a maximum of 32 Gbyte of main memory. The MPC8536E also supports
chip-select interleaving and controller interleaving. There is a variety of MPC8536E SDRAM
configurations. SDRAM banks can be built using DIMMs or directly-attached memory devices. Sixteen
multiplexed address signals provide for device densities of 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1
Gbit, 2 Gbit, and 4 Gbit. Four chip-select signals support up to four banks of memory. Bank sizes range
from 64 Mbyte to 4 Gbyte. Nine column address strobes (Dn_MDM[0:8]) provide byte selection for
memory bank writes. There is cache line and page interleaving between memory controllers.
The MPC8536E can be configured to retain the currently active SDRAM page for pipelined burst accesses.
Page mode support of up to 32 simultaneously open pages can dramatically reduce access latencies for
page hits. Depending on the memory system design and timing parameters, page mode can save 3 to 4
clock cycles for subsequent burst accesses that hit in an active page.
Using ECC, the MPC8536E detects and corrects all single-bit errors and detects all double-bit errors and
all errors within a nibble.
The MPC8536E can invoke a level of system power management by asserting the Dn_MCKE SDRAM
signal on-the-fly to put the memory into a low-power sleep mode.
The DDR controllers offer both hardware and software options for battery-backed main memory. In
addition, the DDR controllers offer an initialization bypass feature for use by system designers to prevent
re-initialization of main memory during system power-on after an abnormal shutdown.
1.3.8
The MPC8536E is designed for low power consumption benefitting equipment manufacturers wishing to
support ENERGY STAR standards. Dynamic power management locally minimizes power consumption
in the doze, nap, or sleep modes. Static power is regulated in the deep sleep mode.
A jog mode feature is provided on the MPC8536E. In jog mode, the e500 core frequency can be adjusted
dynamically while the platform frequency remains unchanged, resulting in optimal device temperature and
power dissipation.
The power management controller (PMC) is responsible for maintaining the device in various low power
modes. The PMC has the following features:
Freescale Semiconductor
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Support high-speed (480 Mbps) and full-speed (12 Mbps)
Support external PHY with UTMI+ low-pin interface (ULPI)
Low standby power
Jog mode support—Adjusts core frequency to optimize power consumption
Fast recovery to restored state
Support for dynamic and static power management to minimize power consumption of idle blocks:
— Doze, nap, and sleep modes for dynamic power management
— Deep sleep mode for static power management
DDR SDRAM Controller
Power Management Controller
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Overview
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