MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1683

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Freescale Semiconductor
Physical memory. The actual memory that can be accessed through the system’s memory
Pipelining. A technique that breaks operations, such as instruction processing or bus
Primary opcode. The most-significant 6 bits (bits 0–5) of the instruction encoding that
Program order. The order of instructions in an executing program. More specifically, this
Protection boundary. A boundary between protection domains.
Protection domain. A protection domain is a segment, a virtual page, a BAT area, or a
Quad word. A group of 16 contiguous locations starting at an address divisible by 16.
Quiesce. To come to rest. The processor is said to quiesce when an exception is taken or a
rA. The rA instruction field is used to specify a GPR to be used as a source or destination.
rB. The rB instruction field is used to specify a GPR to be used as a source.
rD. The rD instruction field is used to specify a GPR to be used as a destination.
rS. The rS instruction field is used to specify a GPR to be used as a source.
Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When it is set, updates the
Reconciliation sublayer. Sublayer that maps the terminology and commands used in the
Reduced instruction set computing (RISC). An
Referenced bit. One of two page history bits found in each
MPC83536E PowerQUICC™ III Integrated Processor Reference Manual, Rev. 1
bus.
transactions, into smaller distinct stages or tenures (respectively) so that a
subsequent operation can begin before the previous one has completed.
identifies the type of instruction.
term is used to refer to the original order in which program instructions are fetched
into the instruction queue from the cache.
range of unmapped effective addresses. It is defined only when the appropriate
relocate bit in the MSR (IR or DR) is 1.
sync instruction is executed. The instruction stream is stopped at the decode stage
and executing instructions are allowed to complete to create a controlled context
for instructions that may be affected by out-of-order, parallel execution. See
Context
condition register (CR) to reflect the result of the operation.
MAC layer into electrical formats appropriate for the physical layer entities.
fixed-length instructions with nonoverlapping functionality and by a separate set
of load and store instructions that perform memory accesses.
processor sets the referenced bit whenever the page is accessed for a read or write.
See also
synchronization.
Page access history
bits.
architecture
page table
characterized by
entry. The
Glossary-7