MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 993

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x1C8
0x248
Offset
0x1BC
0x1C0
0x1C4
0x1FC
0x20C
0x21C
0x23C
0x27C
0x1A4
0x1A8
0x1B0
0x1B4
0x1B8
0x200
0x204
0x208
0x210
0x214
0x218
0x220
0x224
0x228
0x230
0x234
0x238
0x240
0x244
0x280
0x284
–
–
ENLNDAR1—DMA 1 next link descriptor extended address
register
NLNDAR1—DMA 1 next link descriptor address register
ECLSDAR1—DMA 1 current list descriptor extended
address register
CLSDAR1—DMA 1 current list descriptor address register
ENLSDAR1—DMA 1 next list descriptor extended address
register
NLSDAR1—DMA 1 next list descriptor address register
SSR1—DMA 1 source stride register
DSR1—DMA 1 destination stride register
Reserved
MR2—DMA 2 mode register
SR2—DMA 2 status register
ECLNDAR2—DMA 2 current link descriptor extended
address register
CLNDAR2—DMA 2 current link descriptor address register
SATR2—DMA 2 source attributes register
SAR2—DMA 2 source address register
DATR2—DMA 2 destination attributes register
DAR2—DMA 2 destination address register
BCR2—DMA 2 byte count register
ENLNDAR2—DMA 2 next link descriptor extended address
register
NLNDAR2—DMA 2 next link descriptor address register
ECLSDAR2—DMA 2 current list descriptor extended
address register
CLSDAR2—DMA 2 current list descriptor address register
ENLSDAR2—DMA 2 next list descriptor extended address
register
NLSDAR2—DMA 2 next list descriptor address register
SSR2—DMA 2 source stride register
DSR2—DMA 2 destination stride register
Reserved
MR3—DMA 3 mode register
SR3—DMA 3 status register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 15-4. DMA Register Summary (continued)
Register
Access
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
15.3.1.10/15-19
15.3.1.10/15-19
15.3.1.11/15-21
15.3.1.11/15-21
15.3.1.12/15-22
15.3.1.13/15-22
15.3.1.10/15-19
15.3.1.10/15-19
15.3.1.11/15-21
15.3.1.11/15-21
15.3.1.12/15-22
15.3.1.13/15-22
15.3.1.9/15-18
15.3.1.9/15-18
15.3.1.2/15-11
15.3.1.3/15-13
15.3.1.3/15-13
15.3.1.4/15-15
15.3.1.5/15-15
15.3.1.6/15-16
15.3.1.7/15-17
15.3.1.8/15-18
15.3.1.9/15-18
15.3.1.9/15-18
15.3.1.2/15-11
Section/Page
15.3.1.1/15-9
15.3.1.1/15-9
DMA Controller
—
—
15-7