MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 649

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
LGTA/LGPL4/
LUPWAIT/
LAD[0:31]
LA[7:31]
LPBSE
LGPL5
LBCTL
Signal
LFRB/
Table 13-2. Enhanced Local Bus Controller Detailed Signal Descriptions (continued)
I/O
I/O GPCM transfer acknowledge/General-purpose line 4/FCM Flash ready-busy/UPM wait/parity byte select.
I/O Multiplexed address/data bus. For configuration of a port size in BR n [PS] as 32 bits, all of LAD[0:31] must
O
O
O
General-purpose line 5
Data buffer control. The memory controller activates LBCTL for the local bus when a GPCM-, UPM-, or
FCM-controlled bank is accessed. Buffer control is disabled by setting OR n [BCTLD].
Nonmultiplexed address bus. All bits driven on LA[7:31] are defined for 8-bit port sizes. For 32-bit port
sizes, LA[30:31] are don’t cares; for 16-bit port sizes LA[31] is a don’t care.
be connected to the external RAM data bus, with LAD[0:7] occupying the most significant byte lane (at
address offset 0). For a port size of 16 bits, LAD[0:7] connect to the most-significant byte lane (at address
offset 0), while LAD[8:15] connect to the least-significant byte lane (at address offset 1); LAD[16:31] are
unused for 16-bit port sizes. For a port size of 8 bits, only LAD[0:7] are connected to the external RAM.
Meaning
Meaning
Meaning
Meaning
Meaning
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Timing Assertion/Negation—During assertion of LALE, LAD are driven with the RAM address for the
State
State
State
State
State
Asserted/Negated—Input in GPCM or FCM modes used for transaction termination. It may
Asserted/Negated—One of six general purpose signals when in UPM mode, and drives a
Asserted/Negated—The LBCTL pin normally functions as a write/read control for a bus
Asserted/Negated—LA is the address bus used to transmit addresses to external RAM
Asserted/Negated—LAD is the shared 32-bit address/data bus through which external RAM
also be configured as one of six general-purpose output signals when in UPM mode or
as an input to force the UPM controller to wait for the memory/device. FCM uses LFRB
to stall during long-latency read and programming operations, continuing once LFRB
returns high.
When configured as LPBSE, it disables any use in GPCM, FCM, or UPM modes.
Because systems that use read-modify-write parity require an additional memory device,
they must generate a byte-select like a normal data device. ANDing LBS[0:3] through
external logic to achieve the logical function of this byte-select can affect memory access
timing. The LBC provides this optional byte-select signal connection to RMW-parity
devices.
value programmed in the UPM array.
transceiver connected to the LAD lines. Note that an external data buffer must not drive
the LAD lines in conflict with the eLBC when LBCTL is high, because LBCTL remains
high after reset and during address phases.
devices. Refer to
multiplexing.
devices transfer data and receive addresses.
access to follow. External logic should propagate the address on LAD while LALE is
asserted, and latch the address upon negation of LALE. After LALE is negated, LAD are
either driven by write data or are made high-impedance by the eLBC in order to sample
read data driven by an external device. Following the last data transfer of a write access,
LAD are again taken into a high-impedance state.
Section 13.5, “Initialization/Application Information,”
Description
Enhanced Local Bus Controller
for address signal
13-7