MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 333

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-47
8.4.1.42
The memory error extended address capture register, shown in
transaction bits when an error is detected.
Table 8-48
8.4.1.43
The single-bit ECC memory error management register, shown in
for reporting single-bit errors and the number of single-bit errors counted since the last error report. When
the counter field reaches the threshold, it wraps back to the reset value (0). If necessary, software must clear
the counter after it has managed the error.
Freescale Semiconductor
Offset 0xE58
Reset
28–31 CEADDR Captured extended address. Captures the 4 msbs of the transaction address when an error is detected
0–31
0–27
Bits
Bits
W
R
Offset 0xE54
Reset
Figure 8-43. Memory Error Extended Address Capture Register (CAPTURE_EXT_ADDRESS)
0
CADDR Captured address. Captures the 32 lsbs of the transaction address when an error is detected.
Name
Name
W
R
—
describes the CAPTURE_ADDRESS fields.
describes the CAPTURE_EXT_ADDRESS fields.
0
Memory Error Extended Address Capture (CAPTURE_EXT_ADDRESS)
Single-Bit ECC Memory Error Management (ERR_SBE)
Figure 8-44. Single-Bit ECC Memory Error Management Register (ERR_SBE)
Reserved
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-48. CAPTURE_EXT_ADDRESS Field Descriptions
Table 8-47. CAPTURE_ADDRESS Field Descriptions
7
8
SBET
—
All zeros
All zeros
15 16
Description
Description
Figure
Figure
—
8-43, holds the four most significant
8-44, stores the threshold value
23 24
Access: Read/Write
27 28
DDR Memory Controller
Access: Read/Write
CEADDR
SBEC
31
8-59
31