MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1322

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
For the SD card, the identification process starts at a clock rate lower than 400 KHz and the power voltage
higher than 2.7 V, as defined by the card specification. At this time, the SDHC_CMD line output drives
are push-pull drivers instead of open-drain. After the bus is activated, the host requests the card to send
their valid operation conditions. The response to ACMD41 is the operation condition register of the card.
The same command should be sent to all of the new cards in the system. Incompatible cards are placed
into the inactive state. The host then issues the command, ALL_SEND_CID (CMD2), to each card to get
its CID. Cards that are currently unidentified (that is, in ready state), send their CID number as the
response. After the CID is sent by the card, the card goes into the identification state.
The host then issues Send_Relative_Addr (CMD3), requesting the card to publish a new relative card
address (RCA) that is shorter than CID. This RCA is used to address the card for future data transfer
operations. Once the RCA is received, the card changes its state to the standby state. At this point, if the
host wants the card to have an alternative RCA number, it may ask the card to publish a new number by
sending another Send_Relative_Addr command to the card. The last published RCA is the actual RCA of
the card.
The host repeats the identification process with CMD2 and CMD3 for each card in the system until the last
CMD2 gets no response from any of the cards in system.
For MMC operation, the host starts the card identification process in open-drain mode with the
identification clock rate lower than 400 KHz, the power voltage higher than 2.7 V. The open-drain driver
stages on the SDHC_CMD line allow parallel card operation during card identification. After the bus is
activated the host requests the cards to send their valid operation conditions (CMD1). The response to
CMD1 is the wired-OR operation on the condition restrictions of all cards in the system. Incompatible
cards are sent into inactive state. The host then issues the broadcast command All_Send_CID (CMD2),
asking all cards for their unique CID number. All unidentified cards (the cards in ready state)
simultaneously start sending their CID numbers serially, while bit-wise monitoring their outgoing bit
stream. Those cards, whose outgoing CID bits do not match the corresponding bits on the command line
in any one of the bit periods, stop sending their CID immediately and must wait for the next identification
cycle. Since the CID is unique for each card, only one card can successfully send its full CID to the host.
This card then goes into identification state. Thereafter, the host issues Set_Relative_Addr (CMD3) to
assign to this card a relative card address (RCA). Once the RCA is received, the card state changes to the
stand-by state, and the card does not react in further identification cycles, and its output driver switches
from open-drain to push-pull. The host repeats the process, namely CMD2 and CMD3, until the host
receives a time-out condition to recognize completion of the identification process.
20.6.3
Card Access
These sections describe the supported access modes with external cards.
20.6.3.1
Block Write
This section describes the process of writing data to external cards in block mode.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
20-48
Freescale Semiconductor