MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1408

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
The iTD and siTD data structures each describe 8 micro-frames worth of transactions. The host controller
is allowed to cache one (or more) of these data structures in order to reduce memory traffic. There are three
basic caching models that account for the fact the isochronous data structures span 8 micro-frames. The
three caching models are: no caching, micro-frame caching and frame caching.
When software is adding new isochronous transactions to the schedule, it always performs a read of the
FRINDEX register to determine the current frame and micro-frame the host controller is currently
executing. Of course, there is no information about where in the micro-frame the host controller is, so a
constant uncertainty factor of one micro-frame has to be assumed. Combining the knowledge of where the
host controller is executing with the knowledge of the caching model allows the definition of simple
algorithms for how closely software can reliably work to the executing host controller.
No caching is indicated with a value of zero in the Isochronous Scheduling Threshold field. The host
controller may pre-fetch data structures during a periodic schedule traversal (per micro-frame) but will
always dump any accumulated schedule state at the end of the micro-frame. At the appropriate time
relative to the beginning of every micro-frame, the host controller always begins schedule traversal from
the frame list. Software can use the value of the FRINDEX register (plus the constant 1 uncertainty-factor)
to determine the approximate position of the executing host controller. When no caching is selected,
software can add an isochronous transaction as near as 2 micro-frames in front of the current executing
position of the host controller.
Frame caching is indicated with a non-zero value in bit [7] of the Isochronous Scheduling Threshold field.
In the frame-caching model, system software assumes that the host controller caches one (or more)
isochronous data structures for an entire frame (8 micro-frames). Software uses the value of the FRINDEX
register (plus the constant 1 uncertainty) to determine the current micro-frame/frame (assume modulo 8
arithmetic in adding the constant 1 to the micro-frame number). For any current frame N, if the current
micro-frame is 0 to 6, then software can safely add isochronous transactions to Frame N + 1. If the current
micro-frame is 7, then software can add isochronous transactions to Frame N + 2.
Micro-frame caching is indicated with a non-zero value in the least-significant 3 bits of the Isochronous
Scheduling Threshold field. System software assumes the host controller caches one or more periodic data
structures for the number of micro-frames indicated in the Isochronous Scheduling Threshold field. For
example, if the count value were 2, then the host controller keeps a window of 2 micro-frames worth of
state (current micro-frame, plus the next) on-chip. On each micro-frame boundary, the host controller
releases the current micro-frame state and begins accumulating the next micro-frame state.
21.6.9
Asynchronous Schedule
The asynchronous schedule traversal is enabled or disabled through USBCMD[ASE] (asynchronous
schedule enable). If USBCMD[ASE] is cleared, then the host controller simply does not try to access the
asynchronous schedule via the ASYNCLISTADDR register. Likewise, if USBCMD[ASE] is set, the host
controller does use the ASYNCLISTADDR register to traverse the asynchronous schedule. Modifications
to USBCMD[ASE] are not necessarily immediate. Rather the new value of the bit will only be taken into
consideration the next time the host controller needs to use the value of the ASYNCLISTADDR register
to get the next queue head.
USBSTS[AS] indicates status of the asynchronous schedule. System software enables (or disables) the
asynchronous schedule by writing a one (or zero) to USBCMD[ASE]. Software then can poll
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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Freescale Semiconductor