MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 424

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
has been put in service. An interrupt remains in service from the time until the corresponding
end-of-interrupt register (EOI) is written, generating what the PIC considers an EOI signal.
Figure 9-50
9.4.1.2.1
Each interrupt source routed to int is assigned a value through its xVPRn[PRIORITY] field. Priority values
range from 0 to 15, where 15 is the highest. Interrupts are delivered only when the priority of the source
is greater than the destination processor’s CTPR[TASKP]. Therefore, setting xVPRn[PRIORITY] to zero
inhibits that interrupt. Likewise, setting TASKP to 15 prevents the PIC from delivering interrupts to that
core through the int signal. Note that this is the reset value, preventing the PIC from asserting int before
the PIC is configured.
The PIC services simultaneous interrupts occurring with the same priority according to the following
order:
For example, if MSG0, MSG2, and IPI0 are all assigned the same priority and receive simultaneous
interrupts, they are serviced in the following order:
9.4.1.2.2
When the PIC causes int to be asserted, the external interrupt service routine acknowledges the request by
reading that core’s IACK register, which at this point holds the 16-bit vector value for the interrupt source
that generated the request. This is the value programmed in that source’s xVPRn[VECTOR]. Reading
IACK has the following effects:
The interrupt is then considered to be in service. It remains so until the processor core performs a write to
the corresponding EOI. Writing to EOI is referred to as an EOI cycle.
9-54
1. MSG0–MSG7
2. MSI0–MSI7
3. IPI0–IPI3
4. Group A timer0–timer3
5. Group B timer0–timer3
6. IRQ[]/PCI INTx
7. Internal0–internal63
1. MSG0
2. MSG2
3. IPI0
•
•
The int signal for that core is negated, making it possible for another interrupt source to signal an
external interrupt to the core, and more particularly, allowing the PIC to signal a higher-priority
interrupt, as described in
The source that caused that resource is represented in the internal in-service register (ISR).
shows required elements in the interrupt handler
Interrupt Source Priority
Interrupt Acknowledge
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 9.4.1.2.4, “Nesting of
Interrupts.”
Freescale Semiconductor