MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1358

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
There are two operations that can be performed with the ULPI viewport, wakeup and read /write
operations. The wakeup operation is used to put the ULPI interface into normal operation mode and
re-enable the clock if necessary. A wakeup operation is required before accessing the registers when the
ULPI interface is operating in low power mode, serial mode, or carkit mode. The ULPI state can be
determined by reading the sync state bit (ULPISS). If this bit is set, then the ULPI interface is running in
normal operation mode and can accept read/write operations. If the ULPISS is cleared, then read/write
operations will not be able execute. Undefined behavior results if a read or write operation is performed
when ULPISS is cleared. To execute a wakeup operation, write all 32-bits of the ULPI Viewport where
ULPIPORT is constructed appropriately and the ULPIWU bit is set and the ULPIRUN bit is cleared. Poll
the ULPI Viewport until ULPIWU is cleared for the operation to complete.
To execute a read or write operation, write all 32-bits of the ULPI Viewport where ULPIDATWR,
ULPIADDR, ULPIPORT, ULPIRW are constructed appropriately and the ULPIRUN bit is set. Poll the
ULPI Viewport until ULPIRUN is cleared for the operation to complete. For read operations,
ULPIDATRD is valid once ULPIRUN is cleared.
The polling method above can be replaced with interrupts using the ULPI interrupt defined in the USBSTS
and USBINTR registers. When a wakeup or read/write operation completes, the ULPI interrupt is set.
21.3.2.13 Configure Flag Register (CONFIGFLAG)
This EHCI register is not used in this implementation. A read from this register returns a constant of a
0x0000_0001 to indicate that all port routings default to this host controller.
21-24
Offset 0x180
Reset 0
31–1
Bits
15–8
Bits
7–0
0
W
R
31
Name
0
CF
—
ULPIDATRD
0
ULPIDTWR
Reserved.
Configure flag. Always 1 indicating all port routings default to this host.
Name
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-20. ULPI VIEWPORT Field Descriptions (continued)
0
0
Table 21-21. CONFIGFLAG Register Field Descriptions
Figure 21-19. Configure Flag Register (CONFIGFLAG)
After a read operation completes, the result is placed in this field.
When a write operation is commanded, the data to be sent is written to this field.
0
0
0
0
0
0
0
0
—
0
Description
0
0
Description
0
0
0
0
0
0
0
Freescale Semiconductor
0
0
Access: Read only
0
0
0
0
1
CF
1
0