MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 303

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.10
The DDR SDRAM mode configuration register, shown in
DDR’s mode registers.
Table 8-15
8.4.1.11
The DDR SDRAM mode 2 configuration register, shown in
DDR’s extended mode 2 and 3 registers (for DDR2).
Freescale Semiconductor
16–31 SDMODE SDRAM mode. Specifies the initial value loaded into the DDR SDRAM mode register. The range of legal
0–15 ESDMODE Extended SDRAM mode. Specifies the initial value loaded into the DDR SDRAM extended mode register.
Bits
Offset 0x118
Offset 0x11C
Reset
Reset
W
W
R
R
Name
0
0
describes the DDR_SDRAM_MODE fields.
Figure 8-12. DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)
DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)
DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)
Figure 8-11. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)
The range and meaning of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb of ESDMODE, which, in the big-endian convention shown in
ESDMODE[15]. The msb of the SDRAM extended mode register value must be stored at ESDMODE[0].
The value programmed into this field is also used for writing MR1 during write leveling for DDR3, although
the bits specifically related to the write leveling scheme are handled automatically by the DDR controller.
Even if DDR_SDRAM_CFG[BI] is set, this field is still used during write leveling.
values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the lsb
of SDMODE, which, in the big-endian convention shown in
msb of the SDRAM mode register value must be stored at SDMODE[0]. Because the memory controller
forces SDMODE[7] to certain values depending on the state of the initialization sequence, (for resetting the
SDRAM’s DLL) the corresponding bits of this field are ignored by the memory controller. Note that
SDMODE[7] is mapped to MA[8].
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-15. DDR_SDRAM_MODE Field Descriptions
ESDMODE2
ESDMODE
All zeros
All zeros
15 16
15 16
Description
Figure
Figure
Figure
8-11, sets the values loaded into the
8-12, sets the values loaded into the
8-11, corresponds to SDMODE[15]. The
ESDMODE3
SDMODE
Figure
Access: Read/Write
Access: Read/Write
DDR Memory Controller
8-11, corresponds to
31
31
8-29