MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 868

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-111
14.5.3.10 Lossless Flow Control Configuration Registers
When enabled through RCTRL[LFC], the eTSEC tracks location of the last free BD in each Rx BD ring
through the value of RFBPTRn. Using this pointer and the ring length stored in RQPRMn[LEN], the
eTSEC continuously calculates the number of free BDs in the ring. Whenever the calculated number of
free BDs in the ring drops below the pause threshold specified in RQPRMn[FBTHR], the eTSEC issues
link layer flow control. It continues to assert flow control until the free BD count for each active ring
reaches or exceeds RQPRMn[FBTHR]. See section
registers.
14.5.3.10.1 Receive Queue Parameters 0–7 (RQPRM0–PQPRM7)
The RQPRMn registers specify the minimum number of BDs required to prevent flow control being
asserted and the total number of Rx BDs in their respective ring. Whenever the free BD count calculated
by the eTSEC for any active ring drops below the value of RQPRMn[FBTHR] for that ring, link level flow
control is asserted. Software must not write to RQPRMn while LFC is enabled and the eTSEC is actively
receiving frames. However, software may modify these registers after disabling LFC by clearing
RCTRL[LFC]. Note that packets may be lost due to lack of RxBDs while RCTRL[LFC] is clear. Software
can prevent packet loss by manually generating pause frames (through TCTRL[TFC_PAUSE]) to cover
the time when RCTRL[LFC] is clear.
14-120
Offset eTSEC1:0x2_4C00+4 n ;
Reset
13–15
16–17
18–25
26–31
2–12
Bits
0–1
W
R
eTSEC3:0x2_6C00+4 n
0
Name
EL
—
—
—
—
EI
describes the fields of the ATTRELI register.
FBTHR
Reserved
Extracted length. Specifies the number of bytes, as a multiple of 8 bytes, to extract from the receive
frame. The DMA controller uses this field to perform extraction. If cleared, no extraction is performed.
To ensure that EL is a multiple of 8 bytes, these bits should be written with zero.
Reserved
Extracted index. Points to the first byte, as a multiple of 64 bytes, within the receive frame as sent to
memory from which to begin extracting data.
To ensure that EI is a multiple of 8 bytes, these bits should be written with zero.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
7
Figure 14-108. RQPRM Register Definition
Table 14-111. ATTRELI Field Descriptions
8
Figure 14-108
14.6.6.1/14-191
describes the definition for the RQPRMn register.
All zeros
Description
LEN
for the theory of operation of these
Freescale Semiconductor
Access: Read/Write
31