MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 220

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

e500 Core Integration Details
5.3.1
Table 5-2
the SoC revision; it includes a cross-reference to the section in global utilities that contains the
corresponding SVR values. Note that the SVR and PVR can be accessed both as SPRs through the e500
core (see the e500 Reference Manual) and as memory-mapped registers defined by the integrated device.
(See
Register (SVR),”
5-6
HID1
Implementation
Table 5-1. Differences Between the e500 Core and the PowerQUICC III Core Implementation (continued)
Feature
“Section 23.4.1.20, “Processor Version Register (PVR),”
matches the revision codes in the processor version register (PVR) with the core revision and
SoC Revision Core Revision Processor Version Register (PVR) System Version Register (SVR)
Processor Version Register (PVR) and System Version Register
(SVR)
1.1
HID1[PLL_CFG] is implemented as two subfields:
PLL_MODE (HID0[32–33]):
Read-only for integrated devices.
11 Fixed value for this device
PLL_CFG, (HID0[34–39]): The following clock ratios are supported:
0001_00 Ratio of 2:1
0001_01 Ratio of 5:2 (2.5:1)
0001_10 Ratio of 3:1
0001_11 Ratio of 7:2 (3.5:1)
NEXEN, R1DPE, R2DPE, MPXTT, MSHARS, SSHAR, ATS, and MID are not implemented.
On PowerQUICC III devices, ABE must be set to ensure that cache and TLB management instructions operate
properly on the L2 cache.
HID1[RFXE].
If RFXE is 0, conditions that cause the assertion of core_fault_in cannot directly cause the e500 to generate
a machine check; however, PowerQUICC III devices must be configured to detect and enable such conditions.
The following describes how error bits should be configured:
• ECM mapping errors: EEER[LAEE] must be set. See
• L2 multiple-bit ECC errors: L2ERRDIS[MBECCDIS] must be cleared to ensure that error can be detected.
• DDR multiple-bit ECC errors. ERR_DISABLE[MBED] and ERR_INT_EN[MBEE] must be zero and
• PCI. The appropriate parity detect and master-abort bits in ERR_DR must be cleared and the
• Local bus controller parity errors. LTEDR[PARD] must be cleared and LTEIR[PARI] must be set to ensure
L2ERRINTEN[MBECCINTEN] must be set. See
DDR_SDRAM_CFG[ECC_EN] must be one to ensure that an interrupt is generated. See
“Register Descriptions.”
corresponding enable bits in ERR_EN must be set to ensure that an interrupt is generated.
that an parity errors can generate an interrupt. See
Register (LTEIR),”
for further description of the memory-mapped registers.)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 5-2. Device Revision Level Cross-Reference
3.0
and
Section 13.3.1.12, “Transfer Error Attributes Register (LTEATR).”
PowerQUICC III Implementation
0x8021_0030
Section 6.3.1.4, “L2 Error Registers.”
Section 13.3.1.11, “Transfer Error Interrupt Enable
Section 7.2.1.6, “ECM Error Enable Register (EEER).”
and
Section 23.4.1.21, “System Version
23.4.1.21/23-30
Freescale Semiconductor
Section 8.4.1,