MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1056

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
16.3.2
The PCI Local Bus Specification defines the configuration registers contained within the PCI
configuration header from 0x00 through 0x3F.
implemented by the device.
Table 16-49
configuration header registers. Detailed descriptions of these registers are provided in the PCI Local Bus
Specification.
16.3.2.1
The PCI vendor ID register, shown in
16-30
Offset 0x00
Reset
Reserved
Bus Base Class Code
W
R
PCI Bus MAX_LAT
BIST Control
15
0
PCI Configuration Header
in
PCI Vendor ID Register—Offset 0
PCI Bus Arbiter Configuration
Section 16.4.2.11.1, “PCI Configuration Space Header,”
0
PCI Configuration and Status Register Base Address Register (PCSRBAR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Bus Status
Subsystem ID
0
Device ID
Figure 16-24. Common PCI Configuration Header
1
PCI Bus MIN_GNT
Subclass Code
64-Bit High Memory Base Address Register
64-Bit High Memory Base Address Register
64-Bit Low Memory Base Address Register
64-Bit Low Memory Base Address Register
Header Type
1
Figure 16-25. PCI Vendor ID Register
32-Bit Memory Base Address Register
Figure
0
16-25, is used to identify the manufacturer of the part.
Figure 16-24
0
Bus Programming Interface
Vendor ID
1
PCI Bus Interrupt Pin
Bus Latency Timer
x
00
0
lists the common PCI configuration header as
1
Subsystem Vendor ID
PCI Bus Command
PCI Bus Function
0
Vendor ID
provides a summary of the PCI
PCI Bus Capability Pointer 34
1
PCI Bus Interrupt Line
Bus Cache Line Size
Revision ID
0
Freescale Semiconductor
Access: Read only
1
Offset (Hex)
Address
1
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
38
3C
40
44
1
0