MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1518

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
Table 23-18
23.4.1.16 Machine Check Summary Register (MCPSUMR)
Shown in
check interrupt. All MCPSUMR bits function as write-1-to-clear.
Note that other conditions can cause a machine check condition not summarized in MCPSUMR. For
example, uncorrectable read errors cause the assertion of core_fault_in, which may directly cause a
23-26
11–19
21–23
27–31
Bits
0–7
10
20
24
25
26
8
9
Figure
describes PMCDR fields.
TSEC1
TSEC3
Name
USB1
USB2
USB3
SAP
—
—
—
—
—
Register fields designated as write-1-to-clear are cleared only by writing
ones to them. Writing zeros to them has no effect.
23-16, MCPSUMR contains bits summarizing some of the sources of a pending machine
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
0 USB enable clock
1 USB disable clock
0 USB enable clock
1 USB disable clock
0 USB enable clock
1 USB disable clock
Reserved
Debug mode.
0 Enable memory DRAM and Local Bus to be accessed by SAP during sleep or deep sleep
1 Disable memory DRAM, Local Bus and SAP
Reserved
0 eTSEC1 enabled clock
1 eTSEC1 disabled clock
This bit is used in conjunction with tsec1_mac_mpen input signal to the PMC to determine
whether wake on Magic packet or wake on ARP packet is selected.
If wake on ARP packet is selected, the clocks to eTSEC1, AXI2CU, ECM, DDRTQ and DDR
controller will stay ON in low power modes.
Reserved
0 eTSEC3 enabled clock
1 eTSEC3 disabled clock
This bit is used in conjunction with tsec3_mac_mpen input signal to the PMC to determine
whether wake on Magic packet or wake on ARP packet is selected.
If wake on ARP packet is selected, the clocks to eTSEC3, AXI2CU, ECM, DDRTQ and DDR
controller will stay ON in low power modes.
Reserved
USB 1 controller disable clock in low power modes.
USB 2 controller disable clock in low power modes.
USB 3 controller disable clock in low power modes.
Three-speed Ethernet controller 1 disable clock in low power modes.
Three-speed Ethernet controller 3 disable clock in low power modes.
Table 23-18. PMCDR Register Field Descriptions
NOTE
Description
Freescale Semiconductor