MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 653

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Address offsets in the eLBC address range that are not defined in
reading or writing. Similarly, only zero should be written to reserved bits of defined registers, as writing
ones can have unpredictable results in some cases.
Bits designated as write-one-to-clear are cleared only by writing ones to them. Writing zeros to them has
no effect.
13.3.1.1
The base registers (BRn), shown in
memory bank. The memory controller uses this information to compare the address bus value with the
current address accessed. Each register (bank) includes a memory attribute and selects the machine for
memory operation handling. Note that after system reset, BR0[V] is set, BR1[V]–BR7[V] are cleared, and
the value of BR0[PS] reflects the initial port size configured by the boot ROM location power-on
configuration settings.
Table 13-4
Freescale Semiconductor
1
Offset BR0: 0x0_5000
17–18
19–20
Reset 0
0–16
Bits
BR0 has its valid bit (V) set at reset. Thus bank 0 is valid with the port size (PS) configured from cfg_rom_loc[0:3] at power-on
reset. M = 0 for MSEL of GPCM, 1 for MSEL of FCM at boot.The reset value for DECC is determined by cfg_rom_loc. All other
base registers have all bits cleared to zero during reset.
W
R
BR1: 0x0_5008
BR2: 0x0_5010
BR3: 0x0_5018
BR4: 0x0_5020
BR5: 0x0_5028
BR6: 0x0_5030
BR7: 0x0_5038
0
Name
BA
PS
—
0
describes BRn fields.
Base Registers (BR0–BR7)
0
Base address. The upper 17 bits of each base register are compared to the address on the address bus to
determine if the bus master is accessing a memory bank controlled by the memory controller. Used with the
address mask bits OR n [AM].
Reserved
Port size. Specifies the port size of this memory region. For BR0, PS is configured from the power-on reset
configuration setting. For all other banks the value is reset to 00 (port size not defined).
00 Reserved
01 8-bit (supported for GPCM, UPM, FCM)
10 16-bit (supported for GPCM, UPM)
11 32-bit (not supported for FCM)
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
0
0
BA
0
0
Table 13-4. BR n Field Descriptions
Figure 13-2. Base Registers (BR n )
Figure
0
0 0
13-2, contain the base address and address types for each
0
0
0
Description
16 17 18 19 20 21 22
0
0
—
0 P S
Table 13-3
PS
DECC WP
n
n
should not be accessed for
23
0
Enhanced Local Bus Controller
24
0
MSEL
0 M 0
26 27 28 29 30 31
Access: Read/Write
— ATOM — V
0
0
1 V
13-11
1