MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1067

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.2.18 PCI Bus Maximum Latency Register (MAX_LAT)
16.3.2.19 PCI Bus Function Register (PBFR)
The 2-byte PCI bus function register is used to determine how different features of the PCI interface in
bus 0 are configured. This register is in PCI configuration space at offset 0x44.
15–6
16.3.2.20 PCI Bus Arbiter Configuration Register (PBACR)
The PCI bus arbiter configuration register is used to determine the configuration of the PCI bus arbiter.
Freescale Semiconductor
Offset 0x3F
Reset
Bits Name
4–1
5
0
Offset 0x44
Reset
W
R
Bits Name
7–0 MAXLAT Specifies how often the device needs to gain access to the PCI bus (0x00 indicates that this PCI
W
ACL Agent configuration lock. Indicates to an external host whether the local processor is doing internal configuration
PAH PCI agent/host. Read-only. Indicates the reset value of the cfg_host_agt configuration signal.
R
—
—
* = Depends on the state of the reset configuration signals at reset
15
0
Reserved
and must be explicitly set and cleared by the local processor during this time. ACL is set during reset if the
cfg_cpu_boot configuration input selects the CPU as the configuration owner. (See
Configuration.”) This bit is only meaningful in agent mode.
0 PCI interface allows incoming PCI configuration cycles.
1 PCI interface retries all incoming PCI configuration cycles.
Reserved
0 PCI interface is in host mode
1 PCI interface is in agent mode
7
0
controller has no major requirements for the settings of latency timers.)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 16-44. PCI Bus Maximum Latency Register Field Description
Figure 16-45. PCI Bus Maximum Latency Register (MAX_LAT)
0
Table 16-45. PCI Bus Function Register Field Descriptions
0
Figure 16-46. PCI Bus Function Register
0
—
0
0
MAXLAT
All zeros
0
Description
Description
0
0
6
ACL
5
*
0
4
Section 4.4.3.10, “CPU Boot
0
3
—
0
2
Access: Read Only
PCI Bus Interface
Access: Mixed
0
1
0
PAH
16-41
0
*