MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 872

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.11.2 Timer Event Register (TMR_TEVENT)
The eTSEC precision timer implementation can generate additional interrupts that are independent of the
frame based events that controlled via IEVENT. The timer interrupts are not affected by any interrupt
coalescing that may be specified in TXIC/RXIC. Software may poll this register at any time to check for
pending interrupts. If an event occurs and its corresponding enable bit is set in the event mask register
(TEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event register is
cleared by writing a 1 to that bit position. Figure 14-4 describes the definition for the TMR_TEVENT
register.
14-124
30–31
Bits
Offset eTSEC1:0x2_4E04
Reset
Reset
28
29
W
W
R
R
16
0
CKSEL
Name
BYP
TE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-114. TMR_CTRL Register Field Descriptions (continued)
Bypass drift compensated clock
0 64-bit clock counter is incremented on the accumulator overflow
1 64-bit clock counter is directly driven from the external oscillator ignoring accumulator overflow
1588 timer enable. If not enabled, all the timer registers and state machines are disabled.
0 timer not enabled
1 timer enabled and resume normal operation
1588 Timer reference clock source select.
00 External high precision timer reference clock (TSEC_1588_CLK_IN)
01 eTSEC system clock
10 eTSEC1 transmit clock
11 RTC clock input Note that the 1588 reference clock must be no slower than 1/7 the Rx_clk
The default clock select is eTSEC system clock, which is always active when eTSEC is enabled. The
frequency.
user must ensure the corresponding clock source is active before changing the 1588 refclk
selection to external reference, RTC, or TX clock. Selecting an inactive 1588 reference clock may
cause boundedly undefined behavior in the ethernet controller and on accesses to the 1588
registers.
—
Figure 14-111. TMR_TEVENT Register Definition
—
5
ETS2
6
All zeros
All zeros
ETS1
23
7
Description
PP1
24
8
PP2 PP3
25
26
—
27
Freescale Semiconductor
13
—
ALM2 ALM1
Access: w1c
14
15
31