MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 807

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.3.3
The RXIC register enables and configures the operational parameters for interrupt coalescing associated
with received frames.
Table 14-31
1
Freescale Semiconductor
Offset eTSEC1:0x2_4310;
Reset
11–15
16–31
3–10
Bits
The term ‘system clock’ refers to CCB clock/2.
0
1
2
W
R
eTSEC3:0x2_6310
ICEN ICCS —
0
Name
ICEN
ICCS Interrupt coalescing timer clock source.
ICFT
ICTT
—
—
describes the fields of the RXIC register.
1
Receive Interrupt Coalescing Register (RXIC)
Interrupt coalescing enable
0 Interrupt coalescing is disabled. Interrupts are raised as they are received.
1 Interrupt coalescing is enabled. If the eTSEC receive frame interrupt is enabled (IMASK[RXFEN] is set),
0 The coalescing timer advances count every 64 eTSEC Rx interface clocks (TSECn_GTX_CLK).
1 The coalescing timer advances count every 64 system clocks
Reserved
Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines how many frames are received before raising an interrupt. The eTSEC threshold counter is reset
to ICFT following an interrupt. The value of ICFT must be greater than zero avoid unpredictable behavior.
Reserved
Interrupt coalescing timer threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines the maximum amount of time after receiving a frame before raising an interrupt. If frames have
been received but the frame count threshold has not been met, an interrupt is raised when the threshold timer
reaches zero. The threshold timer is reset to the value in this field and begins counting down upon receiving
the first frame having its RxBD[I] bit set. The threshold value is represented in units equal to 64 periods of the
clock specified by RXIC[ICCS]. ICTT must be greater than zero to avoid unpredictable behavior.
2
an interrupt is raised when the threshold number of frames is reached (defined by RXIC[ICFT]) or when
the threshold timer expires (determined by RXIC[ICTT]).
operation.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3
Figure 14-26
ICFT
Figure 14-26. RXIC Register Definition
Table 14-31. RXIC Field Descriptions
describes the RXIC register.
10 11
—
All zeros
Description
15 16
1
. This mode is recommended for FIFO
Enhanced Three-Speed Ethernet Controllers
ICTT
Access: Read/Write
14-59
31