MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 322

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Note that the legal impedance values (from highest impedance to lowest impedance) for DDR2 (1.8 V) are:
A value of 1111 provides the target for half-strength mode when driver calibration is not used.
Note that the legal impedance values (from highest impedance to lowest impedance) for DDR3 (1.5 V) are:
A value of 0000 should be used for default half-strength mode when driver calibration is not used.
Note that the drivers may either be calibrated to full-strength or half-strength.
8-48
5. Clear DDRCDR_1[DSO_MDIC_PZ_OE]
6. After DDRCDR_1[DSO_MDICPZ} is calibrated, set a value of 0000 for
7. Set DDRCDR_1[DSO_MDIC_NZ_OE] to enable the output enable for MDIC[1]
8. After at least 4 cycles, read DDRDSR_1[1]. If the value is 1, then use the next lowest impedance,
9. Clear DDRCDR_1[DSO_MDIC_NZ_OE]
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DDRCDR_1[DSO_MDICNZ]
and read DDRDSR_1[1] again. Once a value of 0 is detected, then leave
DDRCDR_1[DSO_MDICNZ] at the calibrated value
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1110
1010 (default full-strength impedance)
1011
1001
0000
0001
0011
0010
0110
0111 (default full-strength impedance)
0101
0100
1100
1101
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor