MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 842

no-image

MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Enhanced Three-Speed Ethernet Controllers
14.5.3.6.13 Receive Control Frame Packet Counter (RXCF)
Figure 14-67
Table 14-71
14.5.3.6.14 Receive Pause Frame Packet Counter (RXPF)
Figure 14-68
Table 14-72
14-94
16–31
0–15
Bits
Offset eTSEC1:0x2_46B0;
Reset
Offset eTSEC1:0x2_46B4;
Reset
16–31
0–15
Bits
W
W
R
R
Name
RXCF
eTSEC3:0x2_66B4
eTSEC3:0x2_66B0
0
0
describes the fields of the RXCF register.
describes the fields of the RXPF register.
Name
RXPF
describes the definition for the RXCF register.
describes the definition for the RXPF register.
Reserved
Receive control frame packet counter. Increments for each MAC control frame received (PAUSE and
unsupported) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
Figure 14-67. Receive Control Frame Packet Counter Register Definition
Figure 14-68. Receive Pause Frame Packet Counter Register Definition
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
received with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
Receive PAUSE frame packet counter. Increments each time a PAUSE MAC control frame is
Table 14-71. RXCF Field Descriptions
Table 14-72. RXPF Field Descriptions
All zeros
All zeros
15 16
15 16
Description
Description
RXCF
RXPF
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
31
31

Related parts for MPC8536E-ANDROID