MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1265

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
System Bus
CCSR Registers
Host Protocol
Vendor-Specific
Vendor-Specific
FIS Fetched
Command Layer
DMA Controller
FIS Posted
from Memory
to Memory
Host Transport Layer
Link Layer
PHY Control Layer
Host PHY
PCS
SerDes
Figure 19-32. Vendor-Specific BIST Operation
19.4
Transport Layer Architectural Overview
The function of the SATA transport layer is to interface between the command and link layers in the
transmission and reception of FIS.
On the transmit path, the transport layer frames the FIS’s placed into the Tx FIFO. The FIS’s are framed
based on a programmed length for non-data FIS and are a configurable length for data FIS. When the
transport layer is instructed to send a non-data FIS, it employs a retry policy until the far end signals
acceptance of the transmitted FIS.
On the reception path, the transport layer deframes the FIS’s and places them into the Rx FIFO. When an
FIS is received, the transport layer informs the command layer. For a non-data FIS, the FIS is considered
received when the end-of-frame (EOF) is signaled by the link layer and the FIS has been received with a
good CRC. For a short vendor-specific FIS, the FIS is considered as a non-data FIS. For a longer
vendor-specific FIS, the FIS reception is signaled when the RX FIFO reaches its water mark. For a data
FIS, the FIS is considered received when the first word (header) is written into the FIFO.
The receive FIFO is written with data contained in the FIS sent by the link layer. When the data is stable
at the output of the receive FIFO, the command layer can take the data. If the command layer is not ready
to accept the data, the data builds up in the receive FIFO. When the receive FIFO exceeds its threshold,
the transport layer stalls the link layer, which will in turn send HOLD primitives to the far end. This
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor
19-35