MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 49

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Number
23.4.1.20
23.4.1.21
23.4.1.22
23.4.1.23
23.4.1.24
23.4.1.25
23.4.1.26
23.4.1.27
23.4.1.28
23.4.1.29
23.4.1.30
23.4.1.31
23.4.1.32
23.4.1.33
23.5
23.5.1
23.5.1.1
23.5.1.2
23.5.1.3
23.5.1.4
23.5.1.5
23.5.1.6
23.5.1.6.1
23.5.1.6.2
23.5.1.6.3
23.5.1.6.4
23.5.1.6.5
23.5.1.7
23.5.1.8
23.5.1.9
23.5.1.9.1
23.5.1.9.2
23.5.1.10
23.5.1.11
23.5.1.12
23.5.1.13
23.5.1.14
23.5.1.14.1
23.5.1.14.2
23.5.1.14.3
23.5.1.14.4
Freescale Semiconductor
Functional Description................................................................................................. 23-47
Power Management Controller (PMC).................................................................... 23-47
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Processor Version Register (PVR)....................................................................... 23-29
System Version Register (SVR)........................................................................... 23-30
Reset Control Register (RSTCR)......................................................................... 23-30
LBC Voltage Select Control Register (LBCVSELCR) ....................................... 23-31
DDR Clock Disable Register (DDRCLKDR) ..................................................... 23-32
Clock Out Control Register (CLKOCR) ............................................................. 23-33
ECM Control Register (ECMCR) ....................................................................... 23-33
General Control Register (GCR) ......................................................................... 23-34
SerDes1 Control Register 0 (SRDS1CR0) .......................................................... 23-35
SerDes1 Control Register 2 (SRDS1CR2) .......................................................... 23-37
SerDes2 Control Register 0 (SRDS2CR0) .......................................................... 23-39
SerDes2 Control Register 1 (SRDS2CR1) .......................................................... 23-41
SerDes2 Control Register 2 (SRDS2CR2) .......................................................... 23-42
SerDes2 Control Register 3 (SRDS2CR3) .......................................................... 23-44
Overview.............................................................................................................. 23-47
Relationship Between Core and Device Power Management States................... 23-48
CKSTP_IN0/1 is Not Power Management.......................................................... 23-48
Dynamic Power Management.............................................................................. 23-49
Shutting Down Unused Blocks............................................................................ 23-49
Software-Controlled Power-Down States............................................................ 23-49
Power Management Control Fields (e500).......................................................... 23-52
Power-Down Sequence Coordination.................................................................. 23-53
Interrupts and Power Management (e500) .......................................................... 23-54
Snooping in Power-Down Modes (e500) ............................................................ 23-55
Software Considerations for Power Management (e500).................................... 23-55
Requirements for Reaching and Recovering from Sleep State............................ 23-56
Requirements for Reaching and Recovering from Deep Sleep State .................. 23-56
Requirements for Generating Wake-Up Events................................................... 23-57
Doze Mode ...................................................................................................... 23-49
Nap Mode ........................................................................................................ 23-50
Sleep Mode ...................................................................................................... 23-50
Deep Sleep Mode............................................................................................. 23-50
Jog Mode ......................................................................................................... 23-51
Interrupts and Power Management Controlled by MSR[WE] (e500)............. 23-54
Interrupts and Power Management Controlled by POWMGTCSR (e500) ..... 23-55
USB ................................................................................................................. 23-57
GPIO ................................................................................................................ 23-58
Timer................................................................................................................ 23-58
eTSEC Wake-on LAN—Magic Packet ........................................................... 23-58
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