MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1698

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P–P
PCI Local Bus Specification configuration registers
PCI/PCI-X controller
Index-12
signals summary, 17-4
see PCI/PCI-X controller, registers
64-bit/32-bit bus, 16-5
address bus decoding, 16-47
address translation and mapping unit (ATMU)
arbiter configuration (POR), 4-23, 16-5
block diagram, 16-1
burst operations
bus arbitration, 16-5, 16-42
bus protocol, 16-45
clocking, 16-45, 16-50
commands
configuration cycles, 16-58
configuration space addressing, 16-48
data bus width (POR), 4-22
debug mode
error handling, 16-65–16-66
features, 16-4
functional description, 16-42
I/O impedance (POR), 4-22
I/O space addressing, 16-48
initialization/application information, 16-67–??
interrupts
latency timer, 16-36, 16-54, 16-59
memory map/register definition, 16-11
memory space addressing, 16-47
modes of operation, 16-4
see also Signals, PCI Express
inbound windows (4), 2-10, 16-19
outbound windows (4), 16-15
cache wrap mode, 16-47
linear incrementing, 16-47
burst operation, 16-45
command encodings, 16-46
command register, 16-31, 16-59
encodings, 16-46
interrupt-acknowledge transactions, 16-63
special-cycle, 16-64
source and target ID (PCI_AD[63:59]), 25-24
address/data parity, 16-54, 16-65, 16-66
detection and reporting, 16-65
reporting
retry transactions, 16-53
target-abort, 16-53
target-disconnect, 16-53
error enable register, 16-26
IP block revision registers, 17-19
pwr mgmt and message registers, 17-13–17-18
PERR and SERR signals, 16-66
target-initiated termination, 16-53
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
overview, 16-2
performance monitor events
POR configuration, 16-67
power management
register descriptions
signals summary, 16-6
target-abort termination, 16-53
target-disconnect cycles, 16-3, 16-53
target-initiated termination
transactions
agent configuration lock mode, 16-68
agent mode, 16-68
cache wrap mode, 16-47
host mode, 16-68
linear incrementing, 16-47
PCI-X mode
common events, 24-21
special-cycle operations, 16-64
configuration header registers, 16-30–??, 16-59
memory-mapped registers, 16-11
see also Signals, PCI/PCI-X
target-abort error, 16-53
target-disconnect, 16-3, 16-53
selection (POR), 4-22
32-bit memory base address register, 16-37
64-bit high memory base address register, 16-38
64-bit low memory base address register, 16-37
arbiter configuration register (PBACR), 16-41
base address registers, 16-36–16-38
base class code register, 16-35
bus function register (PBFR), 16-41
bus status register, 16-32, 16-49, 16-53, 16-65, 16-66
cache line size register, 16-35
capabilities pointer register, 16-39
command register, 16-31, 16-59
configuration and status register base address
device ID register, 16-31, 16-39
interrupt line register, 16-39
interrupt pin register, 16-40
latency timer register, 16-36
maximum grant (MAX GNT) register, 16-40
maximum latency (MAX LAT) register, 16-41
programming interface register, 16-34
revision ID register, 16-34
subclass code register, 16-35
vendor ID register, 16-30, 16-38
ATMU inbound registers, 16-19–16-23
ATMU outbound registers, 16-15–16-19
by acronym, see Register Index
configuration access registers, 16-14–16-15, 16-60
error management registers, 16-23–16-29
(PCSRBAR), 16-36
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Index