MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1283

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
MSBSEL
RSPTYP
DTDSEL
AC12EN
CCCEN
DPSEL
CICEN
14–15
16–25
Field
10
11
12
13
26
27
28
29
Data present select. Set to indicate that data is present and should be transferred using the SDHC_DAT line. It
is cleared for the following:
Note: In resume command, this bit should be set while the other bits in this register should be set the same as
0 No data present
1 Data present
Command index check enable.
0 Disable. The index field is not checked.
1 Enable. The eSDHC checks the index field in the response to see if it has the same value as the command
index. If it is not, it is reported as a command index error.
Command CRC check enable. The number of bits checked by the CRC field value changes according to the
length of the response. (Refer to RSPTYP[1:0] and
0 Disable. The CRC field is not checked.
1 Enable. The eSDHC checks the CRC field in the response if it contains the CRC field. If an error is detected,
it is reported as a command CRC error.
Reserved
Response type select.
00 No response
01 Response length 136
10 Response length 48
11 Response length 48 check busy after response
Reserved
Multi/single block select. Enables multiple block SDHC_DAT line data transfers. For any other commands, this
bit should be cleared. If this bit is cleared, it is not necessary to set the block count register. (Refer to
Table
0 Single block
1 Multiple blocks
Data transfer direction select. Defines the direction of SDHC_DAT line data transfers. The bit is set by the host
driver to transfer data from the SD card to the eSDHC and it is cleared for all other commands.
0 Write (host to card)
1 Read (card to host)
Reserved
Auto CMD12 enable. Multiple block transfers for memory require CMD12 to stop the transaction. If this bit is
set, the eSDHC issues CMD12 automatically when the last block transfer is completed. The host driver should
not set this bit to issue commands that do not require CMD12 to stop a multiple block data transfer. In particular,
secure commands defined in the Part 3 File Security specification do not require CMD12. In a single block
transfer, the eSDHC ignores this bit.
0 Disable
1 Enable
• Commands using only the SDHC_CMD line (e.g. CMD52)
• Commands with no data transfer but using busy signal on the SDHC_DAT[0] line (R1b or R5b, e.g. CMD38)
20-7.)
when the transfer initially launched.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 20-6. XFERTYP Field Descriptions (continued)
Description
Table
20-8.)
Enhanced Secure Digital Host Controller
20-9